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? 2003 fairchild semiconductor corporation ds500658 www.fairchildsemi.com june 2003 revised june 2003 FIN7216-01 multi-gigabit quad phy FIN7216-01 multi-gigabit quad phy general description the FIN7216-01 is a quad channel 8-bit encoding/decod- ing serializer/deserializer integrated circuit. these trans- ceivers are designed for flexible transfer and recovery of serialized data for use in fibre channel and gigabit ether- net and other applications that require reliable high speed data transfers. the chip operates as an interface between busses, backplanes, or other high bandwidth systems and subsystems. this ic provides full rate operation for maxi- mum data transfer per channel of 1088mb/s (8 bits at 136mhz) as well as half rate operation for a minimum transfer of 392mb/s (8 bits at 49 mhz). the chip consists of a x20/x10 clock generator, four 8b/10b encoders, serializ- ers/deserializers, clock/data recovery units, decoders, and elastic buffers. it can also be used as a quad 10-bit trans- ceiver. applications ? backplane interconnect transceivers proprietary fibre channel gigabit ethernet bus extension link redundancy features quad transceivers data rates between 0.98 gbps to 1.36 gbps and 0.49 gbps to 0.68 gbps ansi x3t11 fibre channel and ieee 802.3z gigabit ethernet compliance aggregate raw data rate of over 8 gigabits per second full duplex pecl tx outputs and rx inputs with redundancy 8b/10b encode and decode per channel optional endec bypass for ten bit interface (tbi) elastic buffers for channel to channel cable deskewing and alignment transmit and receive rate matching via k28.5 symbol idle insertion/deletion align output to local refclk or to recovered clock for received data pecl receive signal detect for both primary and redundant inputs pecl receive signal cable equalization per channel serial transmit to receive loopback mode per channel parallel receive to transmit internal loop- back modes baud rate clock developed from clock multiplier automatic lock to reference clock jtag 1149.1 compliant boundary scan for ttl i/o built-in self test (bist) 3.3v power supply, less than 2.5w 256 pin 27 x 27mm bga package alternate source for vsc7216-01, vsc7217 system level bist from transmit to receive device no external capacitors required optional control of bist through jtag port maximum user generated clock frequency is equal to 1/10 or 1/20 transmit frequency no heat sink required under most operating conditions ordering code: order number package number package description fin721601g bga256a 256-ball thermally-enhanced ball grid array (tbga), jedec mo-149, 1.27mm pitch, 27mm square
www.fairchildsemi.com 2 FIN7216-01 logic diagrams
3 www.fairchildsemi.com FIN7216-01 logic diagrams (continued)
www.fairchildsemi.com 4 FIN7216-01 pin descriptions in this document, each of the four channels are identified as channel a, b, c or d. when discussing a signal on any specific channel, the signal will have the channel letter embedded in the name, e.g., ta(7:0). when referring to the common behav- ior of a signal which is used on each of the four channels, a lower case ? n ? is used in the signal name, e.g., tn(7:0). differ- ential signals (e.g., ptxa+ and ptxa-) may be referred to as a single signal, i.e. ptxa, by dropping reference to the ? + ? and ? - ? . refclk refers either to the pecl/ttl input pair refclkp/refclkn, which can be differential pecl (using both refclkp and refclkn) or single-ended ttl (using refclkp and leaving refclkn open). top view
5 www.fairchildsemi.com FIN7216-01 pin descriptions pin name i/o type pin description 6y, 8u, 7w, 5y, 7v, 7u, 6w, 5w ta(7: 0) i ttl transmit data for channel a, synchronous to refclk, tbca 11u, 11w, 10y, 10w, 10u, 10v, 9y, 9w tb(7:0) i ttl transmit data for channel b, synchronous to refclk, tbcb or tbca 12a, 11c, 11d, 10a, 10b, 10d, 10c, 9a tc(7:0) i ttl transmit data for channel c, synchronous to refclk, tbcc or tbca 8d, 8c, 7b, 5a, 7d, 6b, 6c, 5b td(7:0) i ttl transmit data for channel d, synchronous to refclk, tbcd or tbca 7y 11v 12b 6a c/da c/db c/dc c/dd i ttl control/data for channel n. if c/dn = low, tn(7:0) is used to generate transmit data. if kchar = c/dn = high, special kx.y characters are trans- mitted based upon the value of tn(7:0). if kchar = low and c/dn = high, idle characters are transmitted. when endec = low, this is equivalent to data bit tn8. 8y 12y 12c 8b wsena wsenb wsenc wsend i ttl word sync enable for channel n. asserted high for one cycle to initiate transmission of the word sync sequence as defined in figure 5 and related text. when endec = low, this is equivalent to data bit tn9. 9u 9v 9b 9c tbca tbcb tbcc tbcd i ttl transmit byte clock for channel n. optional input data timing reference for tn(7:0), wsenn and c/dn. 12w kchar i ttl special kx.y character enable. when c/dn is high, kchar controls transmit data. when low, idles are sent. when high, kx.y special char- acters are sent as encoded on tn(7:0). this is intended to be a static input and cannot be changed on a cycle-by-cycle basis. when endec = low, this is equivalent kchar = encdet signal. (see ? decoder bypass mode ? ) 5d 6d 4b tmode0 tmode1 tmode2 i ttl transmit input data timing mode. determines the timing reference for tn(7:0), wsenn and c/dn on all channels as defined in table 3. 20r 17v 18b 20h tberra tberrb tberrc tberrd o ttl transmit buffer error for channel n. when high indicates that the elastic limit of the transmit input skew buffer was exceeded, output timing is same as rn(7:0). a low indicates correct reception of the 256-byte increment- ing pattern in bist mode. 1r, 2r 1m, 2m 1j, 2j 1f, 2f ptxa +/- ptxb +/- ptxc +/- ptxd +/- o pecl primary differential serial tx outputs for channel n. these pins output seri- alized transmit data when ptxenn is high. ac-coupling is recommended 1t, 2t 1n, 2n 1h, 2h 1e, 2e rtxa +/- rtxb +/- rtxc +/- rtxd +/- o pecl redundant differential serial tx outputs for channel n. these pins output serialized transmit data when rtxenn is high. ac-coupling is recom- mended. 4n 4m 4j 4h ptxena ptxenb ptxenc ptxend i ttl primary tx output enable for channel n. when high ptxn+/- is active; when low, ptxn+/- is powered down and the outputs are un-driven. 3p 3n 3h 3g rtxena rtxenb rtxenc rtxend i ttl redundant tx output enable for channel n. when high, rtxn+/- is active; when low, rtxn+/- is powered down and the outputs are un- driven. 18p, 19r, 20u, 20v, 17r, 19u, 20w, 18t ra(7:0) o ttl receive data for channel a. synchronous to rclka/rclkna or refclk as selected by rmode(1:0). 15v, 15u, 18y, 17y, 15w, 14u 16y, 13v rb(7:0) o ttl receive data for channel b. synchronous to rclkb/rclknb, rclka/ rclkna or refclk as selected by rmode(1:0).
www.fairchildsemi.com 6 FIN7216-01 pin descriptions (continued) pin name i/o type pin description 16c, 15c, 15d, 18a, 17a, 15b 14d, 16a rc(7:0) o ttl receive data for channel c. synchronous to rclkc/rclknc, rclka/ rclkna or refclk as selected by rmode(1:0). 20e, 18g, 17g, 19f, 20c, 17f, 19d, 20b rd(7:0) o ttl receive data for channel d. synchronous to rclkd/rclknd, rclka/ rclkna or refclk as selected by rmode(1:0). 17n 18w 17c 19h idlea idleb idlec idled o ttl idle detect for channel n. when high, an idle character has been detected by the decoder and is on rn(7:0). when endec = low, this is equivalent to comdetn (see ? decoder bypass mode ? ) 19p 16v 16d 18h kcha kchb kchc kchd o ttl kx.y character detect for channel n. when high, a special kx.y character has been detected by the decoder and is on rn(7:0). when endec = low, this is equivalent to data bit rn8. 18n 16u 20a 20f erra errb errc errd o ttl error detect for channel n. when high, an invalid 10-bit character or dis- parity error has been detected and the data on rn(7:0) is invalid. when endec = low, this is equivalent to data bit rn9. 20m 19m 17t 20y 18e 17e 17k 18k rclka rclkna rclkb rclknb rclkc rclknc rclkd rclknd o ttl recovered clock outputs for channel n. these outputs are driven from either the channel a or channel n recovered clock, at 1/10 or 1/20 the baud rate, as selected by rmode(1:0) and dual. when unused, rclkn is low and rclknn is high. 6u 4w rmode0 rmode1 i ttl receive output data timing mode. determines the timing reference for all receive channels' rn(7:0), idlen, kchn and errn output data. also for the psdetn, rsdetn and tberrn outputs, as defined in table 7. 1u, 2u 1y, 2y 1a, 2a 1d, 2d prxa+/- prxb+/- prxc+/- prxd+/- i pecl primary differential serial rx inputs for channel n. these pins receive the serialized input data when lbenn(1) is low and rxp/rn is high; other- wise they are unused. they are internally biased at v dd /2 through a 3.2k resistor to the bias voltage. ac-coupling is recommended. 1w, 2w 3y, 4y 3a, 4a 1b, 2b rrxa+/- rrxb+/- rrxc+/- rrxd+/- i pecl redundant differential serial rx inputs for channel n. these pins receive the serialized input data when lbenn(1) is low and rxp/rn is low; oth- erwise they are unused. they are internally biased at v dd /2 through a 3.2k resistor to the bias voltage. ac-coupling is recommended. 4p 3t 4r 3u 4f 3d 4g 3e lbena0 lbena1 lbenb0 lbenb1 lbenc0 lbenc1 lbend0 lbend1 i ttl loop back enable for channel n. these inputs control the channel serial or parallel loopback configuration as described in table 9. 2v 3w 3b 2c rxp/ra rxp/rb rxp/rc rxp/rd i ttl rx input primary/redundant serial input select for channel n. when lbenn(1) is low, this input selects prxn+/- as the rx serial input source when high and rrxn+/- as the serial input source when low. 20p 19v 18d 17j psdeta psdetb psdetc psdetd o ttl primary analog signal detect, channel n. this output goes high when a signal is detected on prxn and low when no signal is detected. output timing is the same as rn(7:0) 17m 18u 19c 20j rsdeta rsdetb rsdetc rsdetd o ttl redundant analog signal detect, channel n. this output goes high when a signal is detected on rrxn and low when no signal is detected. output timing is the same as rn(7:0)
7 www.fairchildsemi.com FIN7216-01 pin descriptions (continued) pin name i/o type pin description 8a 9d refclkp refclkn i pecl refclk differential positive and negative pecl or single-ended ttl inputs. this rising edge of this clock latches transmit data and control into the input register depending on the transmit interface input timing mode (see table 3). it also provides the reference clock, at 1/10th or 1/20th of the baud rate to the pll as selected by dual. if ttl, connect to refclkp but leave refclkn open. if pecl, connect both refclkp and ref- clkn. 1k 1l cap0 cap1 analog loop filter capacitor for clock generation pll. nominally 0.1f, amplitude is less than 3v. see the clock synthesizer section for more details. 5u dual i ttl dual clock mode. when low, refclk and rclkn/rclknn are 1/10th the baud rate. when high, they are 1/20th the baud rate 13w flock i ttl frequency locked mode. when high indicates that each transmit channel's refclk is frequency-locked to the receive channel's word clock. controls rate matching (idle delete/duplicate) logic along with the wsi input as per table 8. 12d bist i ttl built-in self test mode. when high, all transmit channels continuously send a 256 byte incrementing data pattern, and all receive channels signal correct reception of the test pattern with a low on the tberrn outputs. 12v endec i ttl encoder/decoder enable. when high the FIN7216-01 is configured for 8-bit operation, internal 8b/10b encoding is enabled. when low a 10-bit interface is used, internal 8b/10b encoding is bypassed. 12u resetn i ttl resetn input. when asserted low, the transmitter input skew buffers and receiver elastic buffers are re centered, all flip-flops cleared, and all synchronized state machines enter loss_of_sync state. this pin does not reset the internal pll's. 20l wsi i ttl word sync input. used to control channel alignment and idle character insertion/deletion as defined in table 7. 17l wso o ttl word sync output. used to set initial channel word alignment, and to main- tain alignment by controlling idle character insertion/deletion. 15a tck i ttl jtag test access port test clock input 13b tms i ttl jtag test access port test mode select input 14a tdi i ttl jtag test access port test data input 19k tdo o ttl jtag test access port test data output 13a trstn i ttl jtag test access port test logic reset input 14y rsvd i n/a reserved inputs for future use. set high for compatibility reasons. 13y rate i ttl rate mode. when high, FIN7216-01 runs at full data rate (default mode). when asserted low, half-speed data rate is selected. 2l, 4l vdda vdd analog power supply to pll. 2k, 4k vssa gnd analog ground to pll. 11b, 11y, 13d, 15y, 1c, 1v, 20k, 3l, 4d, 4u, 5c, 5v, 8v vddd vdd digital power supply. 11a, 13c, 13u, 19l, 3c, 3k, 3v, 4c, 4e, 4t, 4v, 6v, 7a, 7c, 8w vssd gnd digital ground. 14b, 14w, 17b, 17d, 17h, 17p, 17u, 17w, 18l, 19b, 19e, 19g, 19j, 19n, 19t, 19w vddt vdd ttl output power supply. 14c, 14v, 16b, 16w, 18c, 18f, 18j, 18m, 18r, 18v, 19a, 19y, 20d, 20g, 20n, 20t vsst gnd ttl output ground.
www.fairchildsemi.com 8 FIN7216-01 clock synthesizer the clock synthesizer multiplies the reference frequency of refclk by 10 if the dual input is low, or by 20 if the dual input is high. the capacitor connected between cap0 and cap1 is optional to damp the common-mode noise- especially from the power supply to the clock multi- plier circuit. a 0.1uf or greater differential capacitor should again be connected between cap0 and cap1. these capacitors should be isolated from noisy signals and are shown in figure 1. differential lvpecl or ttl signals can be connected to refclk. when using ttl, connect the input to refclkp and leave refclkn open. for lvpecl inputs, both ref- clkp and refclkn are connected. dc biasing is set internally to vdd/2 on both refclkp and refclkn. figure 1a figure 1b figure 1. loop filter capacitors (optional circuits) as shown in table 1, the rate pin sets the clock generator mode to full or half speed. a high on the rate pin puts the chip in full-speed mode, while a low sets the chip to half-speed. the serial link speed is determined by the ref- clk frequency and clock multiplication factor. table 1. using the rate input to achieve half-speed operation for 500 mb/s and 1 gb/s (note 1) note 1: refer to table 17 for frequency ranges of operation. pin descriptions (continued) pin name i/o type pin description 2p 3r 3m 1p 3j 1g 2g 3f vddpa vddra vddpb vddrb vddpc vddrc vddpd vddrd vdd pecl output power supply for ptxa. pecl output power supply for rtxa. pecl output power supply for ptxb. pecl output power supply for rtxb. pecl output power supply for ptxc. pecl output power supply for rtxc. pecl output power supply for ptxd. pecl output power supply for rtxd. if use of an output is not necessary, leave the power supply pin open. rate pin dual pin clock multiplication factor serial link speed parallel data rate refclk frequency 0 0 x10 500 mb/s 50 mb/s 50 mhz 0 1 x20 500 mb/s 50 mb/s 25 mhz 1 0 x10 1 gb/s 100 mb/s 100 mhz 1 1 x20 1 gb/s 100 mb/s 50 mhz
9 www.fairchildsemi.com FIN7216-01 transmitter functional description transmitter data bus the inputs to each of the four transmit channels include an 8-bit data character, tn(7:0), and the two control pins, c/dn and wsenn. the c/dn input controls the transmission of either a normal data character or a special ? k-character ? . wsenn, when held high for one cycle, starts the transmis- sion of a 16-symbol ? word sync sequence ? used to align the receive channels. the clocking of these data and con- trol inputs is controlled by refclk or the rising edge of tbcn. if tbcn is used, each channel can be clocked by either its own tbcn input or tbca. tmode(2:0) deter- mines the transmit input timing mode. see table 3. table 2. using the rate and dual inputs to achieve the serial link speed operation table 3. transmit interface input timing mode if clocking with tbcn, these inputs must be frequency- locked to refclk. phase-locking is not required, since phase drift between tbcn and refclk is re-centered by a small skew buffer. the resetn input, when asserted low re-centers the buffers, causing the total phase drift to be limited to 180 (one half of one byte time). the channel error output, tberrn, when high indicates that the tbcn to refclk 180 phase drift limit has exceeded the elastic limit of the skew buffer. this means that a channel data byte has been dropped or duplicated. referencing the input timing to refclk eliminates the occurrence of these errors. the tberrn output timing is the same as the receiver outputs, rn(7:0). the various output timing refer- ences are controlled by the state of rmode(1:0). see table 7. figure 2 through figure 4 show the possible relationships between data and control inputs and the selected input tim- ing source. figure 2 shows how refclk is used as an input timing reference. figure 3 and figure 4 show how tbcn is used as an input timing reference. note that the refclk and tbcn inputs are used internally by a pll to generate the appropriate edges to clock the input data. the rising edges of refclk or tbcn provide the reference edge for the phase detection logic. an inter- nal clock is generated at 1/10th or 1/20th of the baud rate of the selected timing reference depending on the state of dual. when dual is high and refclk is the reference timing, the internal active edges are coincident or halfway between the refclk rising edges. tmode rate parallel data dual clock division refclk tbcn clock serial link rate factor frequency frequency speed 000 0 49 - 68 mhz 1 / 2 24.5 - 34 mhz 490 - 680 mbp/s 000 0 49 - 68 mhz 0 / 1 49 - 68 mhz 490 - 680 mbp/s 000 1 98 - 136 mhz 1 / 2 49 - 68 mhz 0.98 - 1.36 gbp/s 000 1 98 - 136 mhz 0 / 1 98 - 136 mhz 0.98 - 1.36 gbp/s 10x 0 49 - 68 mhz 1 / 2 24.5 - 34 mhz 49 - 68 mhz 490 - 680 mbp/s 10x 0 49 - 68 mhz 0 / 1 49 - 68 mhz 49 - 68 mhz 490 - 680 mbp/s 10x 1 98 - 136 mhz 1 / 2 49 - 68 mhz 98 - 136 mhz 0.98 - 1.36 gbp/s 10x 1 98 - 136 mhz 0 / 1 98 - 136 mhz 98 - 136 mhz 0.98 - 1.36 gbp/s 11x 0 49 - 68 mhz 1 / 2 24.5 - 34 mhz 24.5 - 34 mhz 490 - 680 mbp/s 11x 0 49 - 68 mhz 0 / 1 49 - 68 mhz 24.5 - 34 mhz 490 - 680 mbp/s 11x 1 98 - 136 mhz 1 / 2 49 - 68 mhz 49 - 68 mhz 0.98 - 1.36 gbp/s 11x 1 98 - 136 mhz 0 / 1 98 - 136 mhz 49 - 68 mhz 0.98 - 1.36 gbp/s tmode(2:0) input timing reference 000 refclk rising edge 001 010 011 reserved 100 tbca rising edge 101 tbcn rising edge 110 tbca data eye 111 tbcn data eye
www.fairchildsemi.com 10 FIN7216-01 transmitter functional description (continued) figure 2. transmit timing, tmode(2:0) = 000 figure 3. transmit timing, tmode(2:0) = 10x figure 4. transmit timing, tmode(2.0) = 11x 8b/10b encoder the FIN7216-01 has an 8b/10b encoder on each channel. these encoders translate the tn(7:0) 8 bit data into a 10 bit symbol. c/dn and kchar control the transmission of a special kx.y character. see table 4. kchar is intended to be a static input and is not changed cycle-by-cycle like the other transmitter inputs (tn(7:0), c/dn, wsenn). when c/ dn and wsenn are low, encoded data is transmitted. if c/dn is high and kchar is low, a k28.5 idle charac- ter (k28.5 = ? 0011111010 ? or ? 1100000101 ? depending on current running disparity) is transmitted, regardless of the tn(7:0) value. if both c/dn and kchar are high, the tn(7:0) data pattern determines which kx.y character is transmitted. see table 5. all other patterns cause an unde- fined character to be transmitted. note, k28.5+ and k28.5- will force current running disparity to be internally set to negative or positive, respectively. also, a k28.5 + character is a 10b encoding of the k28.5 character chosen from the 8b/10b encoding table column when the current running disparity is positive (i.e. k28.5 = 110000 0101). similarly, a k28.5-character is chosen when the current running disparity is negative. (k28.5 = 001111 1010) table 4. transmit data controls wsenn c/dn kchar raw 8-bit data encoded 10-bit output 0 0 x dx.y encoded dx.y 0 1 0 x idle character (k28.5) 0 1 1 see table 5 special kx.y character 1 x x x 16-character word sync sequence
11 www.fairchildsemi.com FIN7216-01 transmitter functional description (continued) table 5. special characters (selected when c/dn and kchar are high) encoder bypass mode when endec is high, the 8b/10b encoding is enabled. however, when endec is low, the 8b/10b encoding is bypassed and the FIN7216-01 acts as a 10 bit serial trans- mitter. tn0 is transmitted first with c/dn becoming tn8, and wsenn becoming tn9. in this mode, the kchar input becomes encdet. when encdet is high, comma detection and re-synchronization is enabled on all four receivers. refer to the decoder bypass mode section for a description of this mode of operation in the receiver. when endec is low, the transmitter latency is reduced by 10 bit times. this mode is commonly referred to as the ten bit interface (tbi) used in serializers/deserializers for fibre channel and gigabit ethernet applications. word sync generation the FIN7216-01 provides for the generation of channel or word alignment, also known as word sync. if a 4-byte word is input on the four transmit channels for serialization, then the four receive output streams are aligned or synchro- nized so that the same 4-byte data will be transferred to the receive parallel outputs on the same clock. during the word sync sequence, a unique synchronization point in the serial data stream is used to align the receive channels. this pattern is a sequence of 16 consecutive k28.5 idle characters with disparity reversals on the second and fourth characters ( ? i+ i+ i- i- i+ i- i+ i- i+ i- i+ i- i+ i- i+ i- ? or ? i- i- i+ i+ i- i+ i- i+ i- i+ i- i+ i- i+ i- i+ ? ). which sequence is sent is determined by the current running disparity of the transmitter during the serialization of the first idle charac- ter. in order to initiate the transmission of the word sync sequence, wsenn on each channel must be asserted high for one character time on the same clock. see figure 5. during this time, when wsenn is high, the tn(7:0) and c/dn inputs are ignored. additionally, during the next 15 character times, wsenn, tn(7:0), and c/dn are ignored. in figure 5, the word sync sequence is initiated in cycle w1 and transmitted through cycle w16. normal data transmis- sion (or the transmission of another word sync sequence) resumes in cycle d3. this figure is illustrated assuming that input timing is referenced to refclk (e.g., tmode(2:0) = 000) with the dual input low. as long as wsenn remains asserted, another word sync sequence will be generated. figure 5. word sync sequence generation serializer internal to the chip, the 10-bit parallel output of the encoder (or encoder input register if endec is low) is fed into a multiplexer that serializes the transmit data using the pll generated transmit clock. the least significant bit (lsb) is first to transmit. each transmit channel has both primary (ptxn) and redundant (rtxn) output ports. these are gen- erated from differential pecl output buffers running at either 10 or 20 times the refclk rate. these outputs are controlled separately by a primary enable, ptxenn and a redundant enable rtxenn. when either is high, the associated outputs are enabled. when the transmitter out- puts are disabled, the associated output buffers are pow- ered down and consume no power. external resistors are not required on the pecl outputs. code tn(7:0) comment code tn(7:0) comment k28.0 000 11100 user defined k28.5- 101 01101 user defined k28.1 001 11100 user defined k28.6 110 11100 user defined k28.2 010 11100 user defined k28.7 111 11100 test only k28.3 011 11100 user defined k23.7 111 10111 user defined k28.4 100 11100 user defined k27.7 111 11011 user defined k28.5 101 11100 idle k29.7 111 11101 user defined k28.5+ 101 01100 user defined k30.7 111 11110 user defined
www.fairchildsemi.com 12 FIN7216-01 receiver functional description serial data source each of the four receive channels on the FIN7216-01 have primary and redundant input ports associated with corre- sponding serialized transmit outputs. denoted prxn and rrxn, these are the inputs to a differential input buffer. either the prxn or rrxn serial inputs are selected as the data source by the control pin, rxp/rn. if rxp/rn is high, prxn is the data source. however, when the control input lbenn(1:0) = 10, the transmitter loopback data becomes the source and rxp/rn is ignored. see table 6. table 6. serial data source selection signal detection on each receive channel input buffer, there are an analog primary and redundant signal detect output, psdetn and rsdetn, respectively. these outputs can be used as a diagnostics tool for both the selected and non-selected input. psdetn or rsdetn goes high when a signal is sensed on receiver differential input pins. the output is asserted low when no signal is sensed. it is recommended a varying bit pattern be applied to the receiver input when using this function. the signal detect circuitry behaves like a re-triggerable one-shot that is triggered by signal transi- tions, and whose time-out interval ranges from 40 to 80 bit times. the transition density is not checked to make sure that it corresponds to a valid fibre channel and ethernet data stream. the output timing of psdetn and rsdetn is identical to the low-speed receiver outputs, rn(7:0), and is controlled by the value of rmode(1:0). see table 7. receiver equalization it is not uncommon for the data to the receiver inputs prxn/rrxn, to contain a substantial amount of inter sym- bol interference (isi) or deterministic jitter. this interfer- ence can cause the receiver to introduce errors when recovering data. in order to compensate for the cause of error, an equalizer has been added to each receiver input buffer. the equalizer is designed to boost the high fre- quency edge response in order to reduce the effects of isi typically found in copper cables or backplane traces caused by the attenuation of the high frequency content of the signal due to the skin effect. clock and data recovery each receiver channel contain an independent clock recovery unit (cdr). the cdr provides a clean recov- ered clock by automatically locking onto the selected serial input data, extracting the high-speed clock, and re-timing the data. if the data is not present, the cdr will lock to refclk. the recovered clock, rclkn and rclknn, will equal the transmit clock without duty cycle distortion. the cdr performs bit synchronization during sampling of the incoming serial data. if the cdr is not locked onto the serial data, the decoder output data is invalid, and one or more 8b/10b decoding or disparity errors are generated. if the serial data link is disturbed or broken, the cdr requires a specified amount of time to reacquire and lock onto the data. see ac timing characteristics for ? data acquisition lock time ? (table 16). deserializer and character alignment the re-timed serial data from each of the cdr's is fed into the deserializer and converted into a 10 bit character. the receiver recognizes the character boundary in the data pat- tern by detecting a special comma character ('0011111xxx' or '1100000xxx' depending on the current running dispar- ity). it is important to note that this pattern is found in three special fibre characters, k28.1, k28.5 and k28.7, how- ever, k28.5 is chosen as the unique idle character. only k28.1 and k28.5 should be used in normal operation. the k28.7 character should be used for only test and character- ization. character alignment occurs when the deserializer synchro- nizes the 10-bit character boundary to a ? comma ? pattern in the incoming serial data stream. if the receiver identifies a ? comma ? pattern in the incoming data stream which is mis- aligned to the current character boundary the receiver will re-synchronize the recovered data in order to align the data to the new ? comma ? pattern. re-synchronization ensures that the ? comma ? character is output on the internal 10-bit bus so that bits 0 through 9 equal '0011111xxx' or '1100000xxx'. if the ? comma ? pattern is aligned with the current character boundary, re-synchronization will not change the current alignment. re-synchronization is always enabled and cannot be turned off when endec is high. after character re-synchronization the FIN7216-01 ensures that within a link, the 8-bit data sent to the trans- mitting FIN7216-01 will be recovered by the receiving FIN7216-01 in the same bit locations as the transmitter (i.e., tn(7:0) = rn(7:0)). when endec is low, ? comma ? detection and alignment are enabled only if kchar is high. 10b/8b decoder the 10b/8b decoder converts the 10 bit character data from the deserializer into an 8b data byte and three status bits. an out-of band error is generated on the receiver sta- tus bus if the 10 bit character does not represent a valid value. additionally, a disparity error is generated if the cur- rent running disparity of the pattern does not match the expected disparity value. the decoder detects the recep- tion of a k-character and recognizes the unique k28.5 idle from the other k values. the status information is used in conjunction with the loss of synchronization state machine status and fifo error information to provide prior- itized receiver output status information. see table 9. elastic buffer and channel de-skewing the elastic buffer on each receive channel acts as an inter- face between the recovered clock domain and the output clock domain for the decoded data and status information. the decoded data and status information is written into the buffers by the recovered clock, and is read during the selected output clock. this provides for the transfer of decoded data from the timing control of the channel's recovered clock to the timing control of the output clock. the elastic buffers also facilitate channel alignment and rate matching by the insertion/deletion of k28.5 idle char- acters if the channel's recovered clock and output clock are not frequency locked. when initializing the chip or the link, the elastic buffers are re-centered under three conditions. when resetn goes low, the entire chip is initialized and the read/write point- lbenn(1:0) rxp/rn serial data source not equal to 1 0 0 rrxn not equal to 1 0 1 prxn equal to 1 0 x lbtxn loopback from transmitters
13 www.fairchildsemi.com FIN7216-01 receiver functional description (continued) ers are re-centered in each elastic buffer. additionally, the elastic buffer is re-centered when a comma character changes the receive character ? s boundary. lastly, the buffer is re-centered whenever the synchronization point in the word sync sequence is received (see section on word alignment). note that re-centering can result in the loss or duplication of decoded character data and status informa- tion. the user should cause a word sync sequence to re-center all elastic buffers in the event of the change in transmit tim- ing (e.g. phase shifts in tbcn) or phase/alignment shifts in the receiver. this prevents data corruption that could be caused by the shifts. the receiver output recovered data pins is output on pins rn(7:0). the status pins are idlen, kchn and errn. the receive outputs are timed to either refclk, channel as recovered clock (rclka/rclkna), or to its own recov- ered clock (rclkn/rclknn) as selected by rmode (1:0). see table 7. similarly, the transmitter skew buffer error out- puts tberrn and the analog signal detects (psdetn/ rsdetn) are referenced to the selected output timing. when rmode(1:0) = 01 is selected, the refclk leads the valid data window. when rmode(1:0) = 00, refclk is near the center of the valid data window. table 7. receive interface output timing mode the term ? word clock ? will be used for whichever clock, refclk, rclka/rclkna or rclkn/rclknn, is selected as the output timing reference. when rmode(1:0) = 1x each channel's complementary rclkn/ rclknn runs at 1/10th or 1/20th the incoming data baud rate as selected by dual. when rclka/rclkna is selected as the word clock, the other channels' rclkn/ rclknn clocks are duplicates of the a channel clock. when refclk is selected, the decoded data and status information outputs are timed to refclk and each chan- nel's rclkn/rclknn outputs are held in a constant low/ high state, respectively. if dual is high, the data are synchronously clocked out on both positive and negative edges of the selected word clock at 1/20th the baud rate. if dual is low, the data are clocked out on only the rising edge of the word clock at 1/10th the data baud rate. see figure 6 through figure 8. figure 6. receive timing, rmode(1:0) = 00 (refclk centered) figure 7. receive timing, rmode(1:0) = 01 (refclk leading) figure 8. receive timing, rmode(1:0) = 1x rmode(1:0) output timing reference 0 0 refclk (centered) 0 1 refclk (leading) 1 0 rclka/rclkna 1 1 rclkn/rclknn
www.fairchildsemi.com 14 FIN7216-01 receiver functional description (continued) the decoded data is clocked into the elastic buffer by the channel ? s recovered clock and the word clock clocks the data out of the buffers. in order to eliminate rate matching in rmode(1:0) = 0x, the transmitting device ? s refclk must be frequency-locked to the receiver ? s word clock. oth- erwise, the frequency drift between the recovered clock (which is frequency-locked to the transmitter ? s refclk) and the word clock causes the channel ? s elastic buffer to gradually fill or empty. the FIN7216-01 automatically performs rate matching to compensate for any frequency differences between the transmitter ? s refclk and the word clock. the FIN7216-01 does this by deleting or adding idle characters. in order to enable rate matching, flock must be low. however, the configuration of wsi determines whether the channels are individually aligned or aligned in parallel. see ? word align- ment ? section. the system design must guarantee that the frequency at which idles are simultaneously transmitted on each channel accommodates the frequency differences in the system architecture. the idle density requirements must be met, or under-run/over-run errors could result. additionally, a continuous stream of idle characters should be avoided when rate matching is enabled. the idle addition/deletion logic uses the value of the status bits (see table 9.) to detect the k28.5 idle character. the use of continuous idle characters will force the fin7216- 01 into the resync state (see figure 10). the resync mode produces a status bit sequence which has higher pri- ority than the status bit sequence to signal the k28.5 idle characters. the elastic buffers performs at a maximum phase drift of +2 or -2 serial clock bit times between re-synchronizations. this sets a maximum limit on the data ? packet ? length between k28.5 idle characters. this maximum packet length is a function of the differences in frequency of the transmitting device's refclk and receiving device's ref- clk. let ? represent phase drift in bit times, and let 2(pi) repre- sent one full 10-bit character of phase drift. limiting phase drift to two bit times means the following inequality must be satisfied: let l be the number of 10-bit characters transmitted, and let ? f be the frequency offset in ppm. the total phase drift in bit times is given by: a simple expression for maximum packet length as a func- tion of frequency offset is derived by substituting (2) in (1) and solving for l : as an example, if the frequency offset is 200ppm, the max- imum packet length should not be more than 1k bytes. to increase the maximum packet length l , decrease the fre- quency offset ? f. note that if only one k28.5 is transmitted between ? packets ? of data, it might be dropped during com- pensation for phase drift. if an idle is needed between packets, no less than two k28.5 characters must be trans- mitted between packets. word alignment in the word alignment mode on the FIN7216-01, all four tn(7:0) channels on the transmitting device are viewed as a 32-bit word, and the receiving device will recover this identical word. for example, if a transmit pattern was 'abcd', 'efgh', 'ijkl', etc., the receiver should not recover data words as 'abgd', 'efkh', 'ijol', etc. the transmit channels must obtain the input data on a common clock (tmode(2:0) = 000 or 1x0) and the receive chan- nels must present the output data on a common word clock (rmode(1:0) = 0x or 10). the receiver's elastic buffer deskews the four channels and aligns them to a common word clock. the elastic buffer can accommodate up to 6 bit times of channel skew (12 bit times between any two channels) which compensates for circuit imperfections, differences in transmission delay, and jitter. see ? using multiple FIN7216-01s in parallel ? section. word alignment requires that a synchronization point be recognized across the aligned receive channels within the 6 bit time window. in the FIN7216-01, the synchronization point is the first four characters in the word sync sequence (either k28.5+ k28.5+ k28.5- k28.5- or k28.5- k28.5- k28.5+ k28.5+). for example, if channel-to-channel skew is introduced in a 32-bit system, all transmit channels must initiate word sync sequence simultaneously. when the sync point is detected, the recovered data is reposi- tioned in the elastic buffers to align all four channels, and any channel-to-channel skew is removed. thereafter, all normal data characters are word aligned. in this mode one or two of the final twelve k28.5 idle characters in the word sync sequence may be deleted or duplicated in order to correctly recover the transmitted 32-bit word. rate matching is accomplished in the world aligned mode by adding or deleting k28.5 idle characters simulta- neously across the aligned receive channels. the data streams must contain idles inserted simultaneously on all transmit channels according to the idle density require- ments. connecting a device's wsi input to the master wso output enables word alignment. the flock and wsi inputs con- trol whether the device will perform rate matching and whether the matching is done on each individual channel or across parallel aligned channels. when wsi is not con- nected to wso, word alignment is disabled. when either flock is high or wsi is held low, rate matching is dis- abled. see table 8. (1) ? {0.2 x 2 pi) (2) ? = { ? f / 10 6 } x 2 pi l (3) l {0.2 x10 6 }/ ? f
15 www.fairchildsemi.com FIN7216-01 receiver functional description (continued) table 8. word alignment and rate matching control table 8 defines the conditions for word alignment and rate matching. there are essentially four modes of operation. 1. both word alignment and rate matching are disabled (rows 1, 4, and 5). 2. rate matching is enabled with independently operating channels. word alignment is disabled and idles will be duplicated/deleted independently in each channel as needed (row 2). 3. both word alignment and rate matching are enabled. the receive channels are aligned to the master wso, and idle words will be dropped/duplicated across the aligned channels as required (row 3). 4. word alignment is enabled and rate matching is dis- abled. this mode of operation is appropriate for a fre- quency-locked application where it is desired to align the receive channels without altering the received data streams (row 6). using multiple FIN7216-01s in parallel with the use of word alignment mode, multiple fin7216- 01s can be used to provide wider bus widths. in order for word alignment to function properly across multiple devices, the following must occur. each transmit channel ? s input data must share a common clock. also, a common word must be shared clock for all of the receive channels output data. this requires that all transmitting devices use identical refclks, and that tmode(2:0) = 000 (inputs clocked by refclk) or tmode(2:0) = 1x0 (inputs clocked by tbca). if inputs are clocked by tbca, then all transmit- ting devices must use identical tbcas. since all receive channels must use a common word clock, the receiving devices must also use identical refclks and it must be selected as the word clock for all receive channels (rmode(1:0) = 0x). if the transmitting and receiving devices ? refclks are not identical, then rate matching is required (see elastic buffer and channel deskew section). rate matching is accom- plished in word aligned mode by adding or deleting idle characters simultaneously across all aligned receive chan- nels. one FIN7216-01 is chosen as the ? master ? and its' wso output is driven to the wsi inputs of all the receiving FIN7216-01s, including itself. the master provides control via the wso/wsi connection to simultaneously add or drop idles on all FIN7216-01s in the case of transmitters that are not frequency locked to the receivers. wso uses a simple 3-bit serial protocol, synchronous to the master channel's word clock. wso indicates the required synchronization action to all channels of all FIN7216-01s. a steady low level indicates no action. ? 101 ? indicates a word sync event has been identified by the master device's channel a. the relative timing relation- ship between receiving a word sync event by each individ- ual channel and receiving '101' allows the channels to perform the initial synchronization to the master device's channel a. once all of the channels have performed the initial synchronization, a '110' on wso indicates that the next idle encountered in the receive data stream should be deleted by all channels. '111' indicates that an idle should be inserted by all channels after the next idle encountered in the receive data stream. note that channel a of the master device must be an active channel. decoder bypass mode when endec is asserted low, the FIN7216-01 operates as a 10-bit transceiver. the 8b/10b decoder is bypassed and each receiver channel outputs a 10-bit character rn(9:0). the outputs kchn and errn become bit rn8 and rn9, respectively. as previously noted in the ? encoder bypass mode ? section, the kchar inputs becomes enc- det which controls comma detection (comdet) and re- synchronization (byte alignment). when encdet is high, the idlen output becomes comdet and is asserted high when the comma pattern is detected in the current 10-bit data character. when encdet is low, no re-syn- chronization (byte alignment) or comma detection is per- formed. in this mode (endec = 0), only the '0011111xxx' version of the comma + pattern is recognized. the 10-bit interface is commonly found in serializers/deserializers for fibre channel (tr/x3.18 ? 199x) and gigabit ethernet applications. when endec is low, the circuitry that performs word alignment and insertion/deletion of idle characters is dis- abled. since rate matching (see elastic buffer and channel deskewing) is disabled, it is necessary that the word clock source must be frequency-locked to the transmitting device in each channel. this can be done by selecting rmode(1:0) = 11. for other values of rmode(1:0), fre- quency lock must be guaranteed by the system design. when in the x20 clock multiplier mode (dual = 1) and rmode(1:0) = 1x, the output character in each channel containing the comma pattern (0011111xxx) is timed to rclkn/rclknn such that comdet is asserted on the falling of rclkn. this is accomplished without stretching or slivering the recovered clock by adjusting the latency through the elastic buffer. when the comma pattern changes the framing boundary, any data characters prior to a comdet transition on the falling edge of rclkn may be corrupted. flock wsi source word alignment rate matching 00off off 0 1 off enabled, independent channels 0 wso enabled enabled, aligned channels 10off off 11off off 1 wso enabled off
www.fairchildsemi.com 16 FIN7216-01 receiver functional description (continued) figure 9. FIN7216-01 endec flow control receiver state machine each channel has a loss of synchronization state machine (lssm) detects loss of bit, channel, word and word clock synchronization. the three lssm state condi- tions, loss_of_sync; resync; and sync_acquired, are diagrammed in figure 10. upon power-up, the lssm enters loss of sync state. after power-up, the receiver lssm goes into a resync state when the 10-bit data character contains a valid comma character. a valid non-comma character causes the receiver to enter a sync_acquired state, indicating nor- mal receive operation. the lssm will re-enter resync if four consecutive words with comma or a comma indicating a change of framing boundary is transmitted. a loss_of_sync is entered after the invalid transmission counter reaches state 4 (see figure 10). this operation is accomplished using a simple up-down counter that incre- ments/decrements on an invalid/valid 8b/10b encoded transmission. the lssm will stay in loss_of_sync until a valid comma transmission is received; then the state changes back to resync. as noted earlier, the resync state is entered whenever the 10b framing boundary is changed or the word sync sequence is received. when endec is low, the errn, kchn and idlen outputs are re-defined and the decoder and associated lssm logic in each channel is unused. the states of errn, kchn, and idlen are show in table 9. the received data is available in all states of the lssm.
17 www.fairchildsemi.com FIN7216-01 receiver functional description (continued) figure 10. state diagram of the loss of synchronization state machine (see application note for more detail) figure 11. state diagram of the invalid transmission counter link status outputs multiple error conditions are encoded in each channel of the receiver and reported on the output status pins, errn, kchn and idlen. some conditions can occur simulta- neously, so the states are ranked by priority. see table 9. in the case where two or more states apply, the higher pri- ority condition is reported (1 is highest priority). for exam- ple, if both idle detected and resync occur, only a resync is reported because it has higher priority. the current link status asserted on the errn, kchn, and idlen outputs will be timed such that they are synchronous to the appropriate data on the parallel output bus (rn9:0). the only exception to this is the under-run/over-run indica- tion, which is asserted coincident with the duplicated char- acter when an under-run occurs, and is asserted following the deleted character (i.e., on the cycle where the deleted character should have appeared) when overrun occurs.
www.fairchildsemi.com 18 FIN7216-01 receiver functional description (continued) table 9. receiver status signals loopback operation each channel has a loop back enable pin, lbenn(1:0), that controls an internal loopback data path in order to provide for on-chip diagnosis. see table 10. table 10. loopback mode selection when lbenn(1:0) = 10, the serial loopback configuration is selected. in this mode, a path (lbtxn) is enabled between the transmitter ? s serial data and the input of the cdr. this means that parallel data enters the local device on tn(7:0), is encoded, serialized, looped-back, deserial- ized, and decoded when endec is high. this configura- tion allows for the verification of operation of the fin7216- 01 prior to establishing an external connection. lbenn does not affect the data on ptxn/rtxn outputs. when endec is low tn(9:0) is serialized, looped back, and deserialized. when lben(1:0) = 01, parallel loopback is selected. in parallel loopback mode, an internal *refclk copy is used in the receiver as the word clock and tmode(2:0) is internally set to 000, which causes the parallel loopback data from the receiver to be frequency-locked to the device ? s refclk. however, the receiver parallel output data timing that is normally set by the value of rmode(1:0) will not match the normal operation system timing. because of this, the parallel output data should be ignored. when endec is high, the rn(7:0) outputs are looped back to the tn(7:0) inputs (figure 12). wsenn does not have a loopback source and is internally connected to a logic low. kchar is internally connected to a logic high. the c/dn input is internally connected to the kchn output to allow a data character, special character, or idle (k28.5) to be looped back properly. when the link is in the loss of sync (los) or resync states, c/dn is asserted and the data path is set to 0xbc so that an idle will be transmitted. this guarantees that idle and special charac- ters will be correctly looped back along with normal data, and also has the effect of looping back the data received as a normal data character when a disparity error, out-of-band character, or under-run/over-run link status condition occurs. when endec is low, rn(9:0) are looped back to tn(9:0). figure 12. parallel loopback mode operation errn kchn idlen priority link status 0007valid data transmission: a valid 10b data character with correct disparity was received. the correctly decoded version of this character is on rn(7:0) 0011under-run/over-run error: the elastic buffer has not been able to add/drop an idle when required. data on rn(7:0) is invalid 0106kx.y special character detected (not idle): a valid 10b special character with correct disparity was received. the correctly decoded version of this character, per table 4, is on rn(7:0) 0115idle detected: a valid idle character (k28.5) with correct disparity was received. the correctly decoded version of this character, per table 4, is on rn(7:0) 1003out-of-band error detected: a character was received which was not a valid 10b data or control character. data on rn(7:0) is invalid 1014disparity error detected: a valid 10b character was received which did not have the expected disparity. rn(7:0) is invalid 1102loss of synchronization: the receiver state machine is in the loss-of-sync state. data on rn(7:0) is invalid. 1112r esync: the receiver state machine is in the re-synchronization state. data on rn(7:0) is a decoded version of k28.1, k28.5, or k28.7. lbenn(1:0) loopback mode 00 normal operation 01 internal parallel loopback 10 internal serial loopback 11 reserved
19 www.fairchildsemi.com FIN7216-01 receiver functional description (continued) the parallel loopback mode provides for rate-matching in the receiver elastic buffers in the same manner as in nor- mal operation. this avoids receiver over-run/under-run errors in the local device if it and the remote transmitter ? s refclk are not frequency-locked. please note that the lbenn(1:0), rxp/rn, ptxenn, rtxenn and bist inputs must all be configured appropriately in order for end-to-end parallel loopback to function correctly in a user environ- ment. parallel loopback mode is internally disabled when bist mode is enabled. built-in self test operation when bist is asserted high, the built-in self test is enabled, and tmode(2:0) is internally set to a value of 000. endec is internally asserted high after initiation of the bist mode. a word sync sequence is then sent by the transmitter which re-centers the elastic buffers in the receive channel. then, a 256 byte incrementing data pat- tern (prior to encoding) is sent repeatedly by all transmit channels followed by three unique (k28.5) idle charac- ters. note that this incrementing pattern plus three idles will cause both disparities of each data character and the idle character to be transmitted, and contains a sufficient idle density for any application requiring idle insertion/ deletion. if the receiver word clock is not frequency locked to the transmitter ? s refclk, the user conditions the device appropriately to idle insertion/deletion. (see table 8, word alignment and rate matching control) each receiver recognizes this incoming data pattern and any errors will be detected. each receiver indicates that the pattern is received correctly by the assertion of a low on tberrn. a high on tberrn means that an error has occurred. when bist transitions from low to high during the initiation of this mode, tberrn is asserted high. tberrn is reset low once the transmission of one or more idle characters followed by a 256 byte sequential pattern with no errors has occurred. each receive channel functions independently and are not word-aligned. please note that serial loopback mode and receiver output timing mode selection via rmode(1:0) operate independently of bist mode, but bist mode disables parallel loopback mode. figure 13. bist mode operation power up during the power up sequence, the chip initializes, the input skew buffers and the receiver elastic buffers are re- centered, all flip-flops are cleared, and all synchronized state machines enter los.
www.fairchildsemi.com 20 FIN7216-01 absolute maximum ratings (note 2) recommended operating conditions note 2: absolute maximum ratings are dc values beyond which the device may be damaged or have its useful life impaired. the datasheet specifica- tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari- ables. fairchild does not recommend operation outside datasheet specifi- cations. dc electrical characteristics note 3: single-ended measurement results are quoted here. differential techniques used in fibre channel would yield values that are twi ce the magnitude. see diagram below. power supply voltage (any v ddx ) -0.5v to +3.8v pecl differential input voltage -0.5v to v dd +0.5v ttl input voltage -0.5v to 5.5v ttl output voltage -0.5v to v dd +0.5v ttl output current 50 ma pecl output current 50 ma case temperature under bias (t c )-55 o c to +125 o c storage temperature (t stg )-65 o c to +150 o c hbm esd level > 2000v supply voltage (v dd )+3.3v 5% operating temperature range 0 c ambient to 95 c case symbol parameter test conditions min typ max units ttl outputs (rn(7:0), kchn, idlen, errn, rclkn/rclknn, tberrn, psdetn, rsdetn, wso) v oh ttl output high voltage i oh = -1.0 ma 2.4 v v ol ttl output low voltage i ol = +1.0 ma 0.5 v i oz ttl output leakage current when set to high-impedance state through jtag. 100 a ttl inputs (tbcn, tn(7:0), c/dn, wsenn, kchar, rate, bist, lbenn(1:0), tmode(2:0), rmode(1:0), dual, ptxenn, rtxenn, rxp/rn, resetn, endec, wsi, flock, trstn, tdi, tdo, tms, tck) v ih ttl input high voltage 2.0 5.5 v v il ttl input low voltage 0 0.8 v i ih ttl input high current v in = 2.4v 20 a i il ttl input low current v in = 0.5v -100 a pecl inputs (refclk/refclkn) v ih pecl input high voltage v dd - 1.1 v dd - 0.7 v v il pecl input low voltage v dd - 2.0 v dd - 0.8 v i ih pecl input high current v in =v ih(max) 200 a i il pecl input low current v in =v il(min) -20 a ? v in pecl input differential (note 3) 200 mv peak-to-peak voltage swing v cm pecl input v dd -1.5 v dd - 0.7 v common-mode voltage v bias refclkp/refclkn, v dd /2 v prxn+/-, and rrxn+/- internal input bias voltage pecl outputs (ptxn , rtxn ) ? v out pecl differential peak-to-peak | ptxn+ - ptxn- | (note 3) output voltage swing 50 ? to gnd. 500 1300 mv external pull-down resistors not required. pecl inputs (prxn , rrxn ) ? v in pecl input differential 200 1300 mv peak-to-peak voltage swing miscellaneous v dd power supply voltage 3.3v +/- 5% 3.14 3.47 v p d power dissipation maximum at 3.47 v, at max operating frequency, 1.9 2.3 w i dd supply current redundant i/o off, outputs open. 660 ma
21 www.fairchildsemi.com FIN7216-01 ac electrical characteristics in the following tables, ? bc ? refers to encoded bit clock period. for example, at the max rate of 1.36 gbps, bc ? 735 ps figure 14. transmit input timing waveforms with tmode = 000 figure 15. transmit input timing waveforms with tmode = 10x table 11. transmit input ac characteristics with tmode = 000 or tmode = 10x figure 16. transmit input timing waveforms with tmode = 11x (asic-friendly timing) table 12. transmit input ac characteristics with tmode = 11x symbol parameters conditions min max units t 1 input setup time to the rising edge of refclk or tbcn measured between the valid data level of the input and the 1.4v point of refclk or tbcn 1.5 ns t 2 input hold time after the rising edge of refclk or tbcn 1.0 ns symbol parameters conditions min max units t s input skew relative to the rising edge of tbcn or tbda measured between the valid data level of the input and the 1.4v point of tbcn or tbca. bc = bit clock. 2.2 bc
www.fairchildsemi.com 22 FIN7216-01 ac electrical characteristics (continued) figure 17. transmit serial timing waveforms table 13. transmit serial ac characteristics figure 18. receive output timing waveforms with rmode = 00 or 01 table 14. receive outputs ac characteristics with rmode = 00 or 01 symbol parameters conditions min max units t sdr txn+/- rise and fall time measured between 20% to 80% of the valid data level. 330 ps t sdf t lat latency, refclk to tx0 endec = 1 tmode = 000 22bc ? 0.5ns 22bc + 1.0ns bc + ns latency, tbca to tx0 endec = 1 tmode = 10x 36bc + 0.7ns 38bc + 1.8ns latency, tbcb/c/d to tx0 endec = 1 tmode = 101 32bc + 0.7ns 42bc + 1.8ns t j serial data output ieee 802.3z clause 38.69, 192 ps total jitter (p-p) t dj serial data output ieee 802.3z clause 38.69, 80 ps deterministic jitter (p-p) symbol parameters conditions min max units t cq refclk rising edge to ttl output transition rmode = 00; bc = bit clock 2.3 ns - 0 bc 5.5 ns - 0 bc ns t cq refclk rising edge to ttl output transition rmode = 01; bc = bit clock 2.3 ns - 2 bc 5.5 ns - 2 bc ns t qc ttl output transition to refclk rising edge t per - t cq(max) t per - t cq(min) ns
23 www.fairchildsemi.com FIN7216-01 ac electrical characteristics (continued) figure 19. receive output timing waveforms with rmode = 10 or 11 table 15. receive outputs ac characteristics with rmode = 10 or 11 figure 20. rclkn and rclknn timing waveforms with dual = 1 table 16. general receive ac characteristics note 4: the probability of correct data acquisition and recovery is 99% per fc-ph 4.3 section 5.3. figure 21. refclk timing waveforms symbol parameters conditions min max units t cq rclkn/rclknn rising edge to ttl output transition rmode = 10 or 11 -1.25 ns + 4 bc 1.25 ns + 4 bc ns bc = bit clock t qc ttl output transition to rclkn/rclknn rising edge t per - t cq(max) t per - t cq(min) ns dc rclkn/rclknn duty cycle measured at 1.4 v;dual = 1 50% - 1 ns 50% + 1 ns ns symbol parameters conditions min max units t 3 delay between rising edge of rclkn to t rx is the bit period of the incoming 10 x t rx -500 10 x t rx +500 ps rising edge of rclknn data on rx. ? t 3 rclkn to rclknn skew deviation of rclkn rising edge to -500 500 ps delay = 10 ? t3 rclknn rising edge. fbaud nominal delay is 10 bi t 4 period of rclkn and rclknn whether or not locked to serial data, 0.99 x t refclk 1.01 x t refclk independent of dual input. ? t 4 deviation of rclk/rclkn period from whether or not locked to serial data, -1.0 1.0 % refclk period independent of dual input. t rclk = t refclk ? t 4 t r , t f output rise and fall time between v il(max) and v ih(min) into 10pf load 2.4 ns r lat latency from rx0 to refclk or rclk endec = 1, re-center only 68.25bc - 0.6ns 81.25bc + 1.5ns bc + ns endec = x, re-center + drift 48.5bc - 1.6ns 102.5bc + 4.1ns t lock (note 4) data acquisition lock time using k28.5+/k28.5-pattern. 100 bc t jtd receive data total jitter ieee 802.3z clause 38.69, 600 ps tolerance (p-p) tested on a sample basis at 1.25 gbps. d jtd receive data deterministic jitter ieee 802.3z clause 38.69, 370 ps tolerance (p-p) tested on a sample basis at 1.25 gbps.
www.fairchildsemi.com 24 FIN7216-01 ac electrical characteristics (continued) table 17. reference clock requirements serial input rise and fall time ttl input and output rise and fall time receiver input eye diagram jitter tolerance mask figure 22. parametric measurement information serial output load ttl ac output load figure 23. parametric test load circuit symbol parameters conditions min max units fr frequency range dual = 0, rate = 1 98 136 mhz dual = 1, rate = 1 49 68 dual = 0, rate = 0 49 68 dual = 1, rate = 0 24.5 34 fo frequency offset | refclk (tx) - refclk (rx) | = max offset between tx and rx -200 200 ppm device refclks on one serial link. dc refclk duty cycle measured at 1.4v 35 65 % t h , t l refclk and tbc pulse width 3ns t rcr , t rcf refclk rise and fall time between v il(max) and v ih(min) 1.5 ns refclk refclk jitter peak-to-peak jitter at 100 ps jitter FIN7216-01 refclk input.
25 www.fairchildsemi.com FIN7216-01 package thermal considerations the FIN7216-01 is packaged in a 256-pin, 27mm, ther- mally-enhanced bga in a 20x20 array which offers excel- lent electrical characteristics, good thermal performance and small size. this package uses an industry-standard footprint. the package construction is shown in figure 24. figure 24. thermal resistance table 18. thermal resistance moisture sensitivity level this device is rated at with a moisture sensitivity level 3 rating. symbol description value units ca thermal resistance from case-to-ambient in still air including conduction through the leads. 13 c/w ca-100 thermal resistance from case-to-ambient with 100 lfm airflow 11.5 c/w ca-200 thermal resistance from case-to-ambient with 200 lfm airflow 10.5 c/w ca-400 thermal resistance from case-to-ambient with 400 lfm airflow 9.5 c/w ca-600 thermal resistance from case-to-ambient with 600 lfm airflow 8.7 c/w
www.fairchildsemi.com 26 FIN7216-01 multi-gigabit quad phy physical dimensions inches (millimeters) unless otherwise noted 256-ball thermally-enhanced ball grid array (tbga), jedec mo-149, 1.27mm pitch, 27mm square package number bga256a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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